One or more embodiments relate to a method of fabricating a semiconductor device, and more particularly, to a vertical channel transistor within the semiconductor device and a method of fabricating the same.
Recently, the integration density of semiconductor memory devices, particularly in Dynamic Random Access Memory (DRAM), has been increased and is now approaching a gigabit of memory. The gigabit DRAM device is comprised of a plurality of unit cells, each unit cell requiring a pitch of 4F2 (wherein F denotes the minimum feature size). Upon increasing the integration density of the semiconductor device, the size of a transistor constituting a unit cell should be decreased.
The structure of a typical planar-type Metal Oxide Semiconductor (MOS) transistor includes a gate electrode formed on the upper part of the semiconductor substrate and a junction formed within the substrate on both sides of the gate electrode. Accordingly, it is difficult to achieve a planar-type MOS transistor having a unit cell of 4F2 despite having a scaled channel length.
A vertical channel transistor structure has been proposed as a means to overcome the limitations of integrating planar-type MOS transistors.
FIG. 1 is a cross-sectional view showing the detail of a gate electrode of a conventional vertical channel transistor.
As shown in FIG. 1, the conventional vertical channel transistor includes an active pillar pattern 106 having a top pillar pattern 106A and a neck pillar pattern 106B. The neck pillar pattern 106B is a channel part of the transistor, and the top pillar pattern 106A is a drain part of the transistor. A poly-silicon gate electrode 112 is formed by interposing a gate oxide layer 110 surrounding the sidewalls of the neck pillar pattern 106B. A capping layer 108 is formed encapsulating the top pillar pattern 106A and a hard mask pattern 104.
The active pillar pattern 106 is formed by isotropic and anisotropic etching of the silicon substrate 102, while using the hard mask pattern 104 as an etch barrier layer. The poly-silicon gate electrode 112 is formed by depositing a layer of poly-silicon on the resultant pillar pattern structure and, then, etching-back the layer of poly-silicon, while leaving the gate electrode formed in the recesses of the nick pillar pattern 106B.
One of the problems with the conventional vertical channel transistor of FIG. 1 is that the etching may not be properly performed when etching the poly-silicon for a gate patterning. Thus, poly-silicon residue may accumulate to form a bridge between the pillar patterns. This becomes a more serious problem with increased density of the pillar pattern due to increased integration density.
Over-etching is another potential problem with the fabrication of the vertical channel transistor of FIG. 1. As a means for preventing the bridge generation, the poly-silicon layer may be etched too deeply, opening a lower gate oxide layer and partial etching of the substrate below. Thus, a punch phenomenon can occur.
Furthermore, because the gate is made of poly-silicon, a high gate resistance becomes a problem as the density of the resultant structure is increased. That is, characteristics, i.e. conductivity, of the vertical channel transistor begin to degrade.